An implementation of fast polar codes decoder with reducing internal memory and supporting flexible code rate

抄録

This letter proposes a fast simplified successive-cancellation (FSSC) polar decoder architecture, supporting any code rate. With the parameter M, which is the maximum limit length of a special polar node, the authors present a novel scheme for online identification of special node in a polar code. In addition, under the parameter M, the proposed decoder has a well optimized architecture to reduce area, power and energy consumption, that due to require less internal memory using cross-layer calculation and less hardware resources for special node without pipeline technology. Synthesis and post-layout simulate results, based in TSMC 65nm CMOS technology, show that the consumption of hardware resources is reduced by 25%. The architecture and circuit techniques reduce the power to 54.9mW for an energy efficiency of 77.22 pJ/b.