A two-dimension half-select free 12T SRAM cell with enhanced write ability and read stability for bit-interleaving architecture

抄録

This paper proposes a two-dimension half-select free 12T SRAM cell suitable for the bit-interleaving structure. The proposed cell utilizes a data-aware power-cutting method and a decoupled read port as built-in assists to enhance the write margin (WM) and read static noise margin (RSNM) separately. In addition, it realizes two-dimension half-select (HS) free via two technologies, helping bit-interleaving architecture minimize the occurrence of multi-bits soft errors effectively. First, a cross-point-activated wordline successfully isolates the HS disturb in row and column dimensions. Second, a spare pull-up PMOS improves the robustness of column-dimension HS cells, which is lacking by the previous power-cutting structures. Monte Carlo simulations based on SMIC 55nm process confirm the robustness of row and column HS cells. The 12T cell supports a minimum VDD of 0.4V with the proposed methods, 0.3V less than the 6T cell. It improves the WM and RSNM by 2.9× and 14.17× compared to the 6T cell at 0.4V. Meanwhile, it reduces the write power consumption, read power consumption, and leakage power consumption by 52.2%, 4.5%, and 27.7%, respectively, than Chang10T cell at 0.7V.