Exploiting signal skew to reduce delay uncertainty for chiplet interconnects

抄録

High-bandwidth interconnects between chiplets employ parallel interfaces, whose performance is limited by inter-channel crosstalk. In order to reduce the delay uncertainty (jitter) induced by crosstalk, this work analyzes the effect of signal skew and proposes a static skew scheme and a novel dynamic skew scheme. A fast algorithm is also suggested to determine the optimal skew value for the dynamic scheme. The experiment results show that the static scheme can significantly reduce jitter for low-speed buses but fails at high speed. By contrast, the dynamic scheme reduces jitter by about 44% for low-speed buses, reduces the jitter increment due to intersymbol interference by about 71%, and is effective at a higher bus rate. The proposed signal skew schemes require no additional routing overhead.