Low-power and small-area 4-ch 25-Gb/s transimpedance amplifiers in 65-nm CMOS process

抄録

We present an area-efficient and low-power four-channel 25-Gb/s trans-impedance amplifier for an Rx analog front-end (Rx-AFE) on an optical receiver. The proposed circuit features a local negative-feedback trans-impedance amplifier (TIA) to expand the bandwidth. The TIA and post-amplifier use regulated cascode (RGC) topology and two differential amplifier stages with an inductive peaking bandwidth extension technique to acquire 19.6GHz of the -3dB bandwidth and 53.3dBΩ of the gain. We designed the system using a 65-nm CMOS process, and the proposed four-channel Rx-AFE TIAs achieved a small area of 300µm × 800µm per lane. From the measurement results, the differential output voltage was 160mV at 25-Gb/s PRBS31. The test chip has also 85.0mW of power consumption; hence, it achieves 0.85mW/Gb/s of power efficiency.