A low jitter and low reference spur 5GHz PLL with quadrature charge-sampling PD in 28nm CMOS process

Abstract

This paper presents a Quadrature Charge-Sampling Phase Detector PLL (QCSPLL) with low jitter and low reference spur. To address the issues of phase detection gain ambiguity and prolonged re-lock time in sub-sampling PLL, this paper employs a quadrature signal charge sampling gain compensation technique. A phase detector design that utilizes charge sampling and master-slave sampling is adopted, which achieves low reference spur while maintaining low in-band noise. QCSPLL uses a divider to provide four-phase signals. The divider also replaces the VCO buffer while generating the four-phase signal. QCSPLL is realized using a 28nm CMOS process. Simulation results show that the proposed QCSPLL has advantages in re-lock time. The re-lock time is improved by 63%. The prototype achieves 123-fs RMS jitter (10K-100M), -62.4dBc reference spur (without VCO buffer) and -255.2dB FoM.