An efficient GC-LDPC encoder architecture for high-speed NAND flash applications

抄録

Globally-coupled low-density parity check (GC-LDPC) codes have shown great application potential in the error correction of NAND Flash memories. However, the existing LDPC encoder architectures cannot fully use the structure characteristic of GC-LDPC codes. In this letter, focusing on the particular globally-coupled structure, we propose a memory-efficient multiplex-parallel GC-LDPC encoding method and corresponding efficient GC-LDPC encoder architecture. By reusing the local submatrices and optimizing the operation order of piecewise parity bits, the proposed encoding method has low storage overhead and encoding complexity. Then, based on the designed extended shift-register-adder-accumulator (E-SRAA) unit and barrel shifter, we optimize the operator scheduling of the proposed GC-LDPC encoding method when its local encoding is different. The implementation results under various FPGA technologies show that the proposed GC-LDPC encoder architecture achieves a markedly higher throughput-to-resource overhead ratio than existing similar LDPC encoder architectures. Meanwhile, it can meet the bandwidth requirement of ONFI 6.0.