A hybrid interface design based on chip edge connection and inductively coupling connection for 3D stacked chips

Abstract

Conventional three-dimensional packaging chips are based the through-silicon via (TSV) technology. Compared with TSV, inductively coupled interconnect (ICI) ensures reduced costs and increased flexibility. However, some limitations of ICI include high transmission delays and wire-bonding costs. Moreover, it requires the determination of the chip ID during testing. To address these issues, an automatic chip-ID-determining (Auto ID) circuit was combined with a chip edge connect (CEC) technology based on the inter-integrated circuit (IIC) protocol. The experimental results revealed that the CEC technology generated conductive channels at the chip edge, and the Auto ID circuit obtained the chip ID without additional processes. The transmission delay of IIC was one-sixth that of ICI when data were transmitted across 16-layer chips.