A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain

抄録

A wide-frequency all-digital duty cycle corrector with self-adaptive configurable delay chain is proposed. The proposed circuit can detect the alterations of clock frequency and the variations of PVT, and utilizes self-adaptive feedback loop to ensure that the circuit can achieve duty cycle correction within a wide operating frequency range. The test chip is fabricated in 130nm CMOS process, the area occupies 0.016mm². The chip testing results indicate that the correction error is within 2% throughout the input duty cycle from 20% to 80% at the frequency from 260MHz to 1GHz.