Design of memristor-based combinational logic circuits

抄録

The traditional complementary metal oxide semiconductor (CMOS) process technology is approaching its limits due to the continuous shrinking of current semiconductor processes, which has implications for all aspects including device size, performance, power consumption, etc. These aspects also create bottlenecks in traditional Von Neumann computing architecture. As a new type of device that integrates computing and storage functions, the memristor is thus one of the candidates for breaking the mold in the post-Moore era. Here, we study TaO_x-based memristors from a simulation point of view, which is one of the best-performing memristors available. Firstly, we combine the quantum point contact (QPC) model and thermal dissolution mechanism to build a compact Verilog-A model of the TaO_x memristor, which is in good agreement with the experimental characterization data of TaO_x devices. Then, we apply the compact model of TaO_x memristor to logic circuits, and construct a new XOR gate based on the principle of memristor ratio logic (MRL), which can be used to cascade multiple logic gates. Furthermore, we extend these simple logic gates to construct a 1-bit full adder. The results show that the circuit described in this work is much improved in terms of power consumption and integration density compared to conventional CMOS circuits.