A novel current-feedback input buffer with constant Vds control for high-performance ADCs

Abstract

This paper proposes a novel low-voltage and high-linearity input buffer for high-performance Analog-to-Digital Converters (ADCs). The use of current feedback and an auxiliary source follower (SF) is crucial for enhancing linearity, reducing power consumption, and minimizing the circuit area. The proposed buffer, designed in a 40-nm CMOS process, achieves a spurious-free dynamic range (SFDR) exceeding 73.6 dBc at a 1 GS/s sampling rate with a 3.3 pF load capacitance. It occupies 0.00684 mm² and consumes 43 mW at 2.5 V, including bias and common-mode feedback (CMFB) circuits.