2025 Volume 22 Issue 14 Pages 20250196
Superconducting computers can be realized using a Josephson-CMOS hybrid structure, combining the high speed and low power of single-flux quantum (SFQ) logic with the high integration density of CMOS technology. However, reliable interconnection between SFQ and CMOS circuits at cryogenic temperatures remains challenging due to low signal-to-noise ratio (SNR) and interference. To address these challenges, we propose a DC-biased SiGe BiCMOS interface that converts the 0.2 mV output of the SFQ/DC converter (Q2D) to 1.2 V for CMOS memory. A high-impedance voltage amplifier (VA) and a low-impedance transimpedance amplifier (TIA) were designed to optimize signal matching with the Q2D. The interfaces were simulated, fabricated, and tested at 4.2 K to evaluate their performance. Both analytical and experimental results demonstrate that the TIA significantly improves the SNR and enhances noise immunity during static random-access memory (SRAM) read/write operations, making it more effective than the VA for signal matching between the Q2D and CMOS circuits. This work presents a practical solution for SFQ-CMOS interconnection, effectively addressing SNR and interference challenges and contributing to the development of scalable superconducting computing systems.
