A low-overhead resilient circuit with partial two-phase latch

Abstract

Latch-based resilient circuits significantly increases the area overhead to address short-path (SP) issues. This work presents a low-overhead resilient circuit with partial two-phase latch, which selectively inserts negative phase latches to resolve SP issues and reduces the number of insertion points. Furthermore, the monitoring paths reduction method is also proposed by leveraging the time-borrowing capability of latches. The proposed method is implemented on a RISC-V processor, achieving a performance enhancement of up to 73.7% and a power consumption reduction of up to 33%, with only a 6.5% area penalty.