Area and timing optimized 8B/10B pretreating and decoding circuit for JESD204B controller

Jiang Zhong; Yi Shan; Lili Lang; Lin Sun; Yu Liu; Wei Zhong; Yemin Dong

doi:10.1587/elex.21.20240663

LETTER

Area and timing optimized 8B/10B pretreating and decoding circuit for JESD204B controller

Jiang Zhong, Yi Shan, Lili Lang, Lin Sun, Yu Liu, Wei Zhong, Yemin Dong

Author information

Jiang Zhong
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Yi Shan
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Lili Lang
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Lin Sun
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Yu Liu
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Wei Zhong
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
University of Chinese Academy of Sciences
Yemin Dong
State Key Laboratory of Materials for Integrated Circuits, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences
Center of Materials Science and Optoelectronics Engineering, University of Chinese Academy of Sciences

Keywords: JESD204B, 8B/10B decoder, character detection, Serdes, high-speed, low-area

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2025 Volume 22 Issue 2 Pages 20240663

DOI https://doi.org/10.1587/elex.21.20240663

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Abstract

This pretreating and decoding circuit is characterized by high speed and low area. This letter presents the shortest subsequence extraction algorithm as well as redefined and simplified methodology for character detection within single stage, eliminating redundant combinatorial logic and function block. Parallel 8B/10B decoder with mixed structure of decoding and disparity check is also proposed effectively. The circuit, acting as a significant role in JESD204B controller for Gigabit transmission, has been implemented and verified on Xilinx VC707 development kit. This design can achieve lane rate for up to 18.3 Gbps, with increase in frequency by 31% and decrease in area by 12% compared with typical architecture and the optimization of the key components is also greatly remarkable.

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