Area and timing optimized 8B/10B pretreating and decoding circuit for JESD204B controller

抄録

This pretreating and decoding circuit is characterized by high speed and low area. This letter presents the shortest subsequence extraction algorithm as well as redefined and simplified methodology for character detection within single stage, eliminating redundant combinatorial logic and function block. Parallel 8B/10B decoder with mixed structure of decoding and disparity check is also proposed effectively. The circuit, acting as a significant role in JESD204B controller for Gigabit transmission, has been implemented and verified on Xilinx VC707 development kit. This design can achieve lane rate for up to 18.3 Gbps, with increase in frequency by 31% and decrease in area by 12% compared with typical architecture and the optimization of the key components is also greatly remarkable.