An adaptive-compensated charge pump with sub-1-mV ripple and improved transient response for flash-based computing-in-memory

抄録

To achieve efficient parallel computation in the computing-in-memory array, simultaneous activation of multiple wordlines is required to load multiple input feature vectors. Consequently, the load of the charge pump applied to the WL drivers also undergoes frequent changes. This paper presents an adaptive-compensated charge pump for flash-based computing-in-memory, that significantly improves its transient response. The charge pump can be dynamically compensated in response to load variations. This design is implemented in a 55-nm CMOS process with 0.053 mm² layout area. According to the post-layout simulation, the worst steady-state ripple is 0.96 mV at 7-V output voltage and the recovery time (99.9%) is 52 ns at the load change of 25 pF.