Fast-switching and latch-up immunity double-gate SOI lateral IGBT with P-pillar layer

抄録

In this letter, a novel double-gate silicon-on-insulator (SOI) Lateral Insulated Gate Bipolar Transistor with P-pillar (DGP LIGBT) is proposed and investigated by TCAD simulation. The proposed LIGBT structure employs a P-pillar and the N-type carrier stored layer under the P-well, which shows a better compromise between the forward voltage drop (V_on) in the on-state and the turn-off time in the off-state. The proposed DGP LIGBT exhibits the maximum value of the breakdown voltage by virtue of the assisted depletion effect induced by the P-pillar. Meanwhile, the results of the simulation demonstrate that turn-off time of the proposed DGP LIGBT can be decreased by nearly 24.2% and 50.0%, respectively, compared with the double-gate LIGBT (DG LIGBT) and the conventional LIGBT at the same forward voltage drop of 0.91 V. Moreover, the latch-up immunity of the proposed LIGBT structure is significantly improved owing to the optimized hole current path at the cathode.