A code-search-based accuracy calibration technique for delay line based ADC in digital DC-DC converter

Abstract

In digital DC-DC converter systems, factors such as noise, line mismatches, process variations between chips, and common mode level shifts can cause the overall system output voltage to deviate from expectations. This paper proposes a code-search-based accuracy calibration technique for the delay line based ADC in digital DC-DC converter system. By adjusting the calibration module and automatically searching for the maximum output code value, this technique effectively enhances the quantization accuracy of the ADC. The overall chip is fabricated using 0.18 μm CMOS technology, and the ADC occupies an area of 750 μm × 940 μm. Experiment results demonstrate that this technique can improve the ADC’s quantization accuracy to 94.7% and reduce the overall DC-DC loop offset from 2.8% to 0.2%, significantly enhancing the accuracy of the DC-DC output.