Adiabatic SRAM with the large margin of V_th variation by the gradual change of the voltage

抄録

The simplified adiabatic SRAM is proposed which enables gradual charging during writing mode so that problems of electromigration and hot carrier effects can be resolved. For simplicity, we do not use a regenerator circuit for charge recycling in the circuit. In the writing mode, the voltage of the memory cell power line is reduced to ground gradually using a high-resistivity nMOSFET, and we turn off the nMOSFET so that we set the memory cell power line to be in a high-impedance state. Then, we input adiabatic signal from one bit line to charge the memory cell power line to V_DD. This writing method enables gradual discharging and charging. As for reading, the word line voltage is decreased to V_th, or it is changed stepwise while the voltages of bit lines are verified. These reading methods enable the gradual change. With the gradual charge transfer in writing and reading modes, the SRAM can avoid electromigration and hot-carrier effects even in the less-than-45-nm process, while it maintains an operating voltage of 1V or more.