IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
Minimizing the adder cost in multiple constant multipliers
S. Rahimian OmamS. M. FakhraieO. Shoaei
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2006 Volume 3 Issue 14 Pages 340-346


The hardware complexity of digital filters is mainly dominated by the coefficient multipliers. Implementing fixed-point coefficient multiplication as a network of adders, subtractors, and shifters, yields lower power consumption. In such filters the number of adders (and subtractors) determines the implementation cost. The reason is that shifts are implemented as hard-wired inter-block connections and are considered “free”. In transposed implementation of an FIR filter, each input is multiplied by several coefficients. Considering all the coefficients as a multiplier block and omitting the redundancies by sharing the common fundamentals among different coefficients, yields great reduction in the number of arithmetic operations. This paper presents a graph based algorithm to reduce the computational complexity of multiple constant multiplications. Simulation results show that using the proposed method results good improvement in adder cost of multiplier blocks.

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© 2006 by The Institute of Electronics, Information and Communication Engineers
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