In this paper, a performance comparison of several proposed asynchronous pipeline styles is presented. The asynchronous styles include GasP, MOUSETRAP, IPCMOS, LPSR2/1, HC, STFB, LDA, LP2/1, RSPCFB, and NCL. Both 4-bit and 16-bit 4-stage FIFO circuits are designed and simulated utilizing HSPICE. The simulation results are then used to compare the styles in terms of throughput, latency, power dissipation, transistor count, and datapath width. In addition, two figures of merit which relate the energy and the delay of the circuit are utilized in the comparison of the styles. To estimate the throughput and the latency of the circuits, a simple analytical model for the transistor delay is also proposed. The predictions of the analytical model for the throughput and the latency are compared to the simulations results to assess the accuracy of the model.