抄録
This paper describes a 4bit parallel flash Analog-to-Digital converter (ADC) using two sub Flash ADCs and comb-type reference ladder. High speed full flash ADCs have been suffered from input referred noise which is noise itself of analog input or noise inferred from reference ladder. As power supply voltage goes lower and resolution goes higher, noise inferred from reference ladder becomes more critical to ADC's performance. The proposed ADC consists of two parallel sub-ADCs with divided reference ladder to overcome degradation due to small reference voltage step. Simulation results show that the proposed ADC achieves 3.96 effective number of bit (ENOB) for 46MHz input signal and 3.94 ENOB for 1046MHz input signal at 2GHz sampling rate. At 2GSample/s, the current consumption is 45mA including digital logic with 1.8v power supply voltage. The proposed 4bit ADC is designed with 0.18um CMOS technology.
