抄録
A novel low-kickback-noise Class-AB latched comparator utilizing unilateralization technique is presented for high-speed folding and interpolating analog-to-digital converter (ADC).The load transistors are independent with the clock signal. So the comparator can suppress the kickback noise significantly and work at low power supply. Dummy transistors and neutralization technique are also introduced to further reduce the noise. The comparator is simulated in 0.18-µm standard digital CMOS technology. A very low kickback noise voltage of 0.14mV is realized at the differential input voltage of 300mV.The power dissipation is about 202µW at 1.8V supply voltage, 250MHz clock frequency.
