Abstract
There are many challenges inherent in the design of nano-CMOS. This paper describes our recent work relating to the physical design of CMOS circuits. First, in line with variation-aware design, a novel ingenious method of measuring variations in subthreshold characteristics is described. Next, recent RF CMOS issues and approaches to nano-CMOS are discussed. Finally, an on-chip transmission line interconnect developed for global wiring is discussed.
