IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Evaluating the performance of one-dimensional chaotic maps in the network-on-chip mapping problem
Golnar Gharooni-fardAhmad KhademzadeFahime Moein-darbari
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2009 Volume 6 Issue 12 Pages 811-817

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Abstract

Mapping is one of the most critical issues in designing a NoC-based system. A good mapping of an application to a NoC will lead to more traffic among resources, which are physically close on the chip. In this paper, we introduce several one-dimensional chaotic maps for solving the NoC mapping problem. In addition we compare the solution qualities in accordance with different criteria mainly communication cost and convergence time. The results confirm an increase, due to chaotic sequences, in the value of some performance indexes.

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© 2009 by The Institute of Electronics, Information and Communication Engineers
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