New low-voltage small-area mixed-voltage I/O buffer

Abstract

A new mixed-voltage I/O buffer having the characteristics of low-voltage operation and small-area realization is proposed. The proposed I/O buffer provides significantly reduced latency at low supply voltages by eliminating the voltage swing degradation at timing-critical nets. The buffer also provides smaller layout area by avoiding the use of dedicated extra circuits like dynamic gate-bias circuit (DGBC) and hot-carrier prevention circuits (HCPC) to cope with hot-carrier-induced gate-oxide reliability issue. Comparison results in an 80-nm CMOS process indicate that the proposed mixed-voltage I/O buffer achieves 73% reduction on buffer latency, 23% reduction on operating voltage, and 31% reduction on layout area as compared to conventional I/O buffers.