IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
A low power and high density cache memory based on novel SRAM cell
Arash Azizi MazreahMohammad Noorollahi RomaniMohammad Taghi ManzuriAli Mehrparvar
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2009 Volume 6 Issue 15 Pages 1084-1090

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Abstract

Based on the observation that dynamic occurrence of zeros in the cache access stream and cache-resident memory values of ordinary programs exhibit a strong bias towards zero, this paper presents a novel CMOS four-transistor (4T) SRAM cell for very high density and low power cache applications. This cell retains its data with leakage current and positive feedback without refresh cycle. The new cell size is 20% smaller than a conventional six-transistor cell using same design rules and delay access of a cache based on new 4T SRAM cell is 32% smaller than a cache based on 6T SRAM cell. Also the dynamic and static power consumption of new cell is 40% and 20% smaller than 6T SRAM cell, respectively.

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© 2009 by The Institute of Electronics, Information and Communication Engineers
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