A study of clock and data recovery with composite structure of oversampling and gated oscillator for 10Gbit/s subscriber network

Abstract

A composite clock and data recovery circuit based on oversampling and a gated oscillator is proposed. The reduction in the number of multi-phase clocks to be integrated in current silicon technology is discussed. The tolerance to pulse-width variation in a data packet is predicted numerically for an application to 10Gbit/s-based subscriber networks.