In this paper, a new technique is proposed for multiplication of two sampled low frequency analog signals and the result is in digital form. Out of the two signals, one signal is fed to the input of typical second order, ΔΣ Modulator (DSM). The operating period of the DSM circuit is varied directly in proportion to the absolute amplitude of the second analog signal. In this case, the average value of the digital output of quantizer is equal to the product of the analog signals in each sampling period. The dynamic range of input signals and the accuracy of proposed multiplier are better than the conventional CMOS multipliers.