Highly linear mm-wave CMOS low noise amplifier

Abstract

This paper presents a highly linear mm-wave low noise amplifier utilizing a linear attenuating output stage. An analytical method is given for optimum design of this stage by Volterra series. Using a 0.13µum CMOS technology, the IIP3 is improved by more than 10dB reaching to +6dBm, without any extra power consumption. The LNA has a flat gain of 12.7dB with less than ±0.1dB variation from 26 to 35.8GHz and consumes 15.6mW of power. While the input-output matching requirements are well satisfied for this LNA, its noise figure is below 3.7dB over the entire band.