Abstract
A new NoC (network on chip) architecture using lossless data compression and decompression to improve the performance and power efficiency of the on-chip interconnect is proposed. In the proposed NoC scheme, the sender compresses the data to be transferred in order to reduce the number of data packets and the receiver decompresses the encoded data to restore the original data. For the lossless compression and decompression, we have implemented a hardware CODEC based on a Golomb-Rice algorithm. According to the experimental results using a cycle-accurate NoC simulator, the proposed scheme could significantly improve the performance and power efficiency of the conventional NoC architecture.
