This paper proposes a unified solution to reduce test power and test volume for test-per-scan schemes. With the self-testing using MISR and Parallel SRSG (STUMPS) architecture and the developed reconfigurable Johnson counter, the proposed test pattern generator (TPG) applies two transition sequences to all scan chains, and the primary inputs of the circuit under test (CUT) keep unchanged at most times. Therefore, the switching activities both in the combinational block and in scan chains can be reduced simultaneously. If the generated test vectors that do not contribute to fault coverage are filtered out, the remaining deterministic patterns show the favorable features of high compressible and low-test power. Simulation results on ISCAS'89 benchmarks demonstrate that the proposed TPG imposes negligible impact on test length and power overhead of the CUT.