A novel digital calibration technique for pipelined ADCs

Abstract

This paper presents a digital background calibration technique to correct the capacitors mismatch, gain error and gain nonlinearities of 1.5bit/stage pipelined ADCs. The calibration technique uses a modified structure for the ADC stages, the skip-fill method and LMS algorithm and does not require any accurate calibration signal and any added analog circuitry; just some digital circuits are needed to fill the skipped samples and realize the LMS algorithm. Circuit level simulation results in a 90-nm CMOS technology are provided for a 12-bit 80-MS/s pipelined ADC to verify the effectiveness of the proposed calibration technique.