2010 Volume 7 Issue 23 Pages 1752-1759
This paper presents a low-energy prime-field elliptic-curve cryptography (ECC) hardware processor, suitable for low-power and/or energy-efficient applications and systems. The ECC processor is obtained by power-optimizing a previously reported design. The optimization is performed by making the power consumption profile of the processor as uniform as possible, in an attempt to increase the secondary battery life between discharge and recharge cycles and to create resistance against simple power attacks (SPA) to the cryptosystem by analyzing the power dissipation trace of the hardware. The optimized ECC processor performs a single 192-bit scalar multiplication in 652ms consuming only 22.3µJ at a clock frequency of 1MHz. This indicates, in addition to the more uniform power consumption, a 13% reduction in the energy and power consumption compared to the previously reported design.
