Novel FPGA-based pipelined floating point FFT processor

Abstract

Two novel architectures for pipelined floating point fast Fourier transform on FPGA are presented. The new radix-2² two-path delay feedback (R2²TDF) architecture leads to 50% area saving for floating point complex adders compared with the radix-2² single-path delay feedback (R2²SDF) architecture. Besides a new hybrid architecture is presented which mixes the R2²TDF and R2²TDF butterfly structures and is flexible and efficient for FPGA implementation.