Abstract
We have been developing a Josephson/CMOS hybrid memory, which enables sub-nanosecond access time, in order to overcome a memory bottleneck in single-flux-quantum (SFQ) digital systems. In our previous study, we obtained the access time of about 1.2ns in a 16-kb hybrid memory system using a 0.35µm CMOS process, but observed unexpected double peaks in histograms of access-time measurements. In this study, we designed a 64-kb hybrid memory system using a 0.18µm CMOS process. We considered that the double peak effect is due to parasitic capacitances at the bonding pad of Josephson and CMOS chips and reduced them in the new design. Measured access time is about 1.4ns, which agrees well with simulation results. The double peaks in the histogram were completely removed in the new results.
