抄録
A new technique to adjust the duty cycle of the output clock by adopting a pulsewidth control loop (PWCL) in dual-slope combination is presented. Correcting both rising and falling slopes simultaneously in their combination leads to a simple way for a wide correction range. Furthermore, the duty cycle can be easily adjusted to a desired value by setting up the programmable current sources in the charge pump. A generic circuit is suggested, and its validity is verified in a 0.13-µm CMOS technology under 1.2V supply. The simulated results with Spectre exhibit the integral nonlinearity (INL) of less than 2% for the output duty-cycle range from 6.25% to 93.75% with the consideration of process, voltage, and temperature (PVT) variation.
