IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Fully parallel comparator for the moduli set {2n,2n-1,2n+1}
Shiva Taghipour EivaziMehdi HosseinzadehOmid Mirmotahari
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2011 Volume 8 Issue 12 Pages 897-901

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Abstract

A novel circuit based on sign detection is introduced in this paper which uses the subtraction for comparing two numbers without carrying out a full comparison and conversion. Thus, the proposed schema decreases the delay significantly using only a little redundant hardware in contrast to previous works. Also the time complexity of the new design has the best results comparing to the previous work.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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