IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
High performance VLSI design of run_before for H.264/AVC CAVLD
Jongwoo BaeJinsoo ChoBaekhyun KimJonghyen Baek
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JOURNALS FREE ACCESS

2011 Volume 8 Issue 12 Pages 950-955

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Abstract

High-performance algorithm and VLSI architecture for H.264/AVC context-adaptive, variable-length decoder (CAVLD) run_before computations are proposed to reduce the computation cycles. The run_before values of input symbols are estimated if they are zeroes in parallel. By skipping the estimation step when long symbols starting with ‘000’ are input, the architecture was drastically simplified while maintaining high performance. Experimental results showed that the performance for run_before computations improved by 68% on average when four symbols were estimated in parallel in comparison with sequential estimation of the symbols. The area of run_before is increased by 23% by the proposed architecture.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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