IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
A parallel power amplifier with load impedance transformation for optimized low power performance
Geunyong LeeJongsoo Lee
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2011 Volume 8 Issue 12 Pages 956-962


This paper presents analytic expressions for T-type chain matching network synthesis of the power amplifier (PA) to enhance the performance at low output powers via a load impedance adjustment. Here, a parallel power amplifier for WCDMA B1 (1920-1980MHz) based on an InGaP/GaAs hetero-junction bipolar transistor (HBT) is utilized, which has a fully integrated matching network on a printed circuit board (PCB). As a result, the power amplifier shows a 38.7% power added efficiency (PAE), and a -37dBc adjacent channel leakage power ratio (ACLR) at 27.5dBm output during high power mode operation, and 17.6% PAE with a 22mA quiescent current and a -40.7dBc at a back-off output power of 17dBm during low power mode.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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