A test pattern generation method with high compression ratio

Abstract

This paper proposes a test pattern generation and compression method to reduce test volume for VLSI testing. Unlike traditional approaches, the proposed scheme predefines linear relationships between vectors or within a vector of a test sequence firstly. Then, it determines test patterns by fault simulation. Therefore, patterns of a deterministic test set keep the predefined linear relationships, and can be highly compressed. Simulation results on ISCAS'89 benchmarks demonstrate that the proposed method can significantly reduce the data size with high fault coverage.