Efficient implementation of FPGA based central pattern generator using distributed arithmetic

抄録

A scheme for efficient hardware implementation of central pattern generators (CPGs) on Field Programmable Gate Arrays (FPGAs) is proposed. A revised distributed-arithmetic (DA) algorithm is applied to the implementation to maximize the utilization of look up tables (LUTs) in FPGAs. The proposed scheme performances satisfactory experiment results which have correlation coefficients of 0.99 with simulation ones. In the mean time, it demonstrates 74% reduction in LUTs consumption, 75% in registers and 100% in embedded multipliers.