IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
LETTER
Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process
Hyunju HamToshimasa MatsuokaJun WangKenji Taniguchi
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2011 Volume 8 Issue 6 Pages 353-359

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Abstract

A stochastic signal detection circuit that uses a non-linearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500MS/s.

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© 2011 by The Institute of Electronics, Information and Communication Engineers
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