Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Hyunju Ham; Toshimasa Matsuoka; Jun Wang; Kenji Taniguchi

doi:10.1587/elex.8.353

IEICE Electronics Express

Online ISSN : 1349-2543
ISSN-L : 1349-2543

LETTER

Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Hyunju Ham, Toshimasa Matsuoka, Jun Wang, Kenji Taniguchi

Author information

Keywords: signal detection, comparator, mismatch, CMOS

JOURNAL FREE ACCESS

2011 Volume 8 Issue 6 Pages 353-359

DOI https://doi.org/10.1587/elex.8.353

Details

Abstract

A stochastic signal detection circuit that uses a non-linearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500MS/s.

Content from these authors

Favorites & Alerts

Corresponding author

Register with J-STAGE for free!