Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Hyunju Ham; Toshimasa Matsuoka; Jun Wang; Kenji Taniguchi

doi:10.1587/elex.8.353

LETTER

Design of a 500-MS/s stochastic signal detection circuit using a non-linearity reduction technique in a 65-nm CMOS process

Hyunju Ham, Toshimasa Matsuoka, Jun Wang, Kenji Taniguchi

著者情報

キーワード: signal detection, comparator, mismatch, CMOS

ジャーナルフリー

2011 年 8 巻 6 号 p. 353-359

DOI https://doi.org/10.1587/elex.8.353

詳細

抄録

A stochastic signal detection circuit that uses a non-linearity reduction technique is designed using a 65-nm CMOS process. The fabricated chip demonstrates the feasibility of stochastic signal detection at 500MS/s.

責任著者(Corresponding author)

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