抄録
In this paper, a multiple valued register file (MVRF) with 2-read 1-write circuit is designed in TSMC Low Power 65nm CMOS. High VTH and Low VTH transistors are organized together to realize a multiple-threshold Literal Gate, and then connect with pass-gates to implement ternary valued register file cell. The information density of the proposed MVRF cell achieves a 61% improvement compared to a standard 6T SRAM, and more than 140% improvement compared to a binary register file. In addition, the quantity of the word line and bit line reduces about 33% compare to a standard 6T SRAM, which also improves the system information density. An 8×8 MVRF array have been designed and simulated in terms of power, speed and cell stability. Simulation results show that the MVRF array operates at 1.0GHz, consuming 1.2mW at 1.2V.
