抄録
In this paper, we propose a critical-path based timing driven FastPlace, named TimFastPlace, which uses an iterative critical path-based weighting model to optimize the critical path delay at the equation solving stage. Experimental results on several industry cases and ISCAS89 cases show that we are able to obtain up to 30.83% Worst Negative Slack (WNS), an average of 23.42% WNS and 18.87% Total Negative Slack (TNS) improvement in circuit delays at an average of 2.54% wire length increase. Besides, runtime is kept at the same level as FastPlace.
