IEICE Electronics Express
Online ISSN : 1349-2543
ISSN-L : 1349-2543
A novel methodology for speeding up IC performance in 32nm FinFET
Hung Viet NguyenMyunghwan RyuYoungmin Kim
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2012 Volume 9 Issue 4 Pages 227-233


This paper presents a novel methodology for IC speed-up in 32nm FinFET. By taking advantage of independently controlling two gates of IG-FinFET, we develop the boosting structures that can improve the signal propagation on interconnect significantly. Furthermore, the circuit area and power dissipation issues are also taken into account. With the addition of boosting path, the full booster can reduce the delay of interconnect as much as 50% while consuming merely more than 18% of power. In the high-speed and low-power IC designs, the proposed boosting structure gives circuit designers several options in the trade-off between the power consumption and high performance which play an important role in application-specific integration circuits in the 22nm node and beyond.

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© 2012 by The Institute of Electronics, Information and Communication Engineers
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