IEICE Electronics Express
Online ISSN : 1349-2543
LETTER
Low-power dual-supply clock networks with clock gating and frequency doubling
Hoi-Jin LeeJong-Woo KimTae Hee HanJae Cheol SonJeong-Taek KongBai-Sun Kong
Author information
JOURNALS FREE ACCESS

2012 Volume 9 Issue 6 Pages 502-508

Details
Abstract

Low-power dual-supply clock networks based on novel level-converting clock gating cells are presented. The proposed clock networks achieve a substantial power saving with mitigated timing constraints on gated clocks. They also allow pulse-based flip-flops used at leaf clock nodes to work with no pulse generators, resulting in more power saving and area reduction. The proposed dual-supply clock networks were designed in a 32nm CMOS technology. The evaluation results indicated that the proposed clock-gating cells have up to 24.8% smaller power with 74.3% reduced latency and 17.5% reduced area. They also indicate that the power consumption of the proposed clock networks was reduced by up to 30.3%.

Information related to the author
© 2012 by The Institute of Electronics, Information and Communication Engineers
Previous article Next article
feedback
Top