Abstract
A novel implementation of the complete all-digital M-b successive approximation register-controlled delay-locked loop (SAR DLL) is presented with wide-range, reduced hardware overhead and close to 50% duty cycle. The proposed SAR DLL adopts the digital-controlled resettable delay line to achieve the ultra fast-locking and eliminate the harmonic-locking issue of the conventional SAR ADDLL in wide-range application. All design units are first described in verilog, and then mapped to silicon using the SMIC 0.18µm CMOS Artisan standard cell library.
