High performance sparse matrix-vector multiplication on FPGA

Abstract

This paper presents the design and implementation of a high performance sparse matrix-vector multiplication (SpMV) on field-programmable gate array (FPGA). By proposing a new storage format to compress the indexes of non-zero elements by exploiting the substructure of the sparse matrix, our SpMV implementation on a reconfigurable computing platform with a multi-channel memory subsystem is capable of obtaining similar performance by using a single FPGA to that of a highly optimized BFS implementation on a commercial heterogeneous system containing four FPGAs.